1. Field of the Invention
The present invention relates to a process of manufacturing a semiconductor device. More particularly, it relates to a process of manufacturing a semiconductor device such as a gate array device, application specified (AS) IC and the like, for which reduction of turn around time (hereinafter referred to as TAT) for the manufacture has been demanded.
2. Description of Related Art
Gate array devices and ASICs are user-specified semiconductor devices obtained by providing a master chip comprising a plurality of transistors formed on a semiconductor substrate and connecting necessary transistors through wirings.
Reduction of TAT has recently been demanded for such semiconductor devices. On the other hand, as users require higher function, the devices are miniaturized by using submicron process and provided with a multi-layered wiring of 3 to 6 layers, which makes TAT lengthy.
Accordingly, methods have been proposed for reducing TAT while dealing with the miniaturization and the multi-layered wiring and retaining highly reliable connection. For example, Japanese Unexamined Patent Publication No. HEI 6(1994)-236875 discloses the following method.
First, a plurality of contact holes are opened in advance and filled with a conductive layer 222 to almost entire depth thereof. Then the remaining openings of the contact holes are filled with an insulating film 223 as shown in FIG. 6(a). Next, after a user""s specification is decided, the insulating film 223 in the contact holes desiring to form a wiring layer is removed by photolithography and etching. Then a wiring layer 217 is formed thereon as shown in FIG. 6(b). In the figures, reference numeral 201 is a device isolation region, 202 is a gate insulating film, 203 is a gate electrode, 204 and 205 are low concentration impurity regions, 207 and 208 are high concentration impurity regions, and 211 is an interlayer insulating film.
In this method, the conductive layer is buried in the contact holes. This allows preventing an increase in contact resistance and a decrease in connection reliability that are liable to accompany with the device miniaturization (i.e., an increase in the aspect ratio of the contact holes).
However, this method separately requires the selective removal of the insulating film from the contact holes and the formation of a metal wiring in the removed region after the user""s specification is decided. Therefore two photolithography steps and two etching steps must be performed, which makes TAT lengthy.
Further, the metal wiring generates level difference thereon. The level difference complicates the formation of an interlayer insulating film having a flat top surface between the metal wiring and a multi-layered wiring to be formed thereon. This level difference caused by the metal wiring is generally formed in a height of about 0.5 xcexcm, though it varies depending on the density of current flowing therethrough. It prevents the formation of the multi-layered wiring.
Accordingly, as the semiconductor devices are further miniaturized and the wiring are more multi-layered, there will arise keen demands for:
(a) retaining highly reliable connection by filling the contact holes with the conductive layer;
(b) reducing the level difference caused by the metal wiring as small as possible to improve flatness and to easily form the wiring layer on the metal wiring; and
(c) reducing TAT.
In consideration of the above subjects, the inventor of the present invention has established a method of manufacturing a semiconductor device capable of burying the conductive layer in the contact holes and reducing the level difference caused by the wiring layer, without taking lengthy TAT. Thus, the present invention has been achieved.
According to the present invention, provided is a process of manufacturing a semiconductor device comprising:
a step of forming an interlayer insulating film so as to cover a plurality of semiconductor elements formed on a semiconductor substrate,
a step of forming openings in predetermined regions of the interlayer insulating film on the semiconductor elements in a manner of penetrating only halfway through the interlayer insulating film,
a dual damascene step of forming contact hole by removing the interlayer insulating film remaining under the predetermined ones of the openings, thereby forming simultaneously openings for burying a wiring layer which include upper portions of the predetermined openings,
a step of forming a conductive layer on the interlayer insulating film to fill at least the contact holes and the openings for burying the wiring layer; and
a step of forming contact plugs and a buried wiring layer by removing the conductive layer on the interlayer insulating film.
These and other objects of the present application will become more readily apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.